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Altera_Forum's avatar
Altera_Forum
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12 years ago

close loop at Test Bench

Hi ,

i want to close loop back at the Test bench between the transmitted data from transmitter to the receiver .

both transmitter and receiver implemented at VHDL and they are known to the top .

a,b - output ports

c,d - input ports

i instantiate the output from transmitter entity - serial_out is the output of the generator entity inside transmitter entity :

serial_out => a ;

i instantiate the output from top entity :

a => b ;

i instantiate the output b to input of the top from test bench to close the loop :

b => c ;

i instantiate the input from top entity :

c => d ;

i instantiate the input from receiver entity - serial_in is the input of the receiver sub entity inside receiver entity:

d=> ser_in ;

after simulation at modelsim there are error massage :

" Unknown formal identifier " for a,b,c,d .

what did i do wrong ?

do i need to instantiate the program deferentially ?

file attached .

14 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Hi ,

    The last scheme i added was general .

    I added now the scheme of my project and code is relevant for this scheme (attached file ) .

    The code of : Test Bench , Top, Tx , Rx , PN_Generator , Meta_Fix is also attached at files .

    all of them are entities at different files .

    The names of I/O ports at visio are the same at code .

    The errors at Modelsim are :

    1.after compiling testbench :

    ** Error: D:/Final Project/Technical/Top/simulation/modelsim/TestBench.vhd(49): (vcom-1035) Formal port "ser_in1" has OPEN or no actual associated with it.

    2.after compiling top :

    ** Error: D:/Final Project/Technical/Top/hdl/top.vhd(30): (vcom-1484) Unknown formal identifier "ser_in1".

    3.After compiling Rx

    ** Error: D:/Final Project/Technical/Top/hdl/Rx.vhd(33): (vcom-1484) Unknown formal identifier "ser_in".

    When compile the transmitter alone the result were proper serial data at ser_out .
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    --- Quote Start ---

    attached the rest of the files .

    --- Quote End ---

    you haven't connected ser_in of top.

    you only connected ser_out to ser_in1.

    ser_out is now driving ser_in1 but then ser_in1 must drive ser_in of top
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Hi kaz ,

    i did connect between ser_in1 to ser_in .

    look at row 30 at top file :

    ser_in1 => ser_in , --in std_logic

    thanks for your assistance .
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    --- Quote Start ---

    Hi kaz ,

    i did connect between ser_in1 to ser_in .

    look at row 30 at top file :

    ser_in1 => ser_in , --in std_logic

    thanks for your assistance .

    --- Quote End ---

    you are mixing up between names.

    ser_in is not a port, you are just driving it from internal signal that is not driven.

    just connect as I told in my above post.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    you need to connect ser_in1 of your rx module to serial_in1 port of top.

    Then in testbench, connect ser_in1 to say "temp" signal then connect temp to ser_out.

    In your testbench then I assume you drive ser_out with some data internally to be received by Rx
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    ok ,

    i connect : ser_in1=>ser_in at test bench file and now it compile without errors.

    i connect : ser_in => data_in at top file ( ser_in1 is the input port to the top ) .

    i declare data_in as a signal at the top file - signal data_in : std_logic; and now top file compile without errors .

    At the Rx file ser_in as input port ,

    At the Rx file i declare data_in as signal and connect : Data_in=> Data_in_D .

    There are 11 errors at Rx file after compiling .

    one of the errors is :

    1. ** Error: D:/Final Project/Technical/Top/hdl/Rx.vhd(34): (vcom-1136) Unknown identifier "Data_in_D".

    Data_in_D is the input port to MetaFix - declared at Rx file . i tried to declare it as a signal at Rx file but still it has the same error .

    2. The rest of the errors related to the other signals at Rx Entity/file :

    ** Error: D:/Final Project/Technical/Top/hdl/Rx.vhd(45): (vcom-1484) Unknown formal identifier "reg_in_signal1".

    ** Error: D:/Final Project/Technical/Top/hdl/Rx.vhd(53): (vcom-1136) Unknown identifier "cmp_in_Tx".

    ** Error: D:/Final Project/Technical/Top/hdl/Rx.vhd(54): (vcom-1136) Unknown identifier "cmp_in_Rx".

    ** Error: D:/Final Project/Technical/Top/hdl/Rx.vhd(53): (vcom-1484) Unknown formal identifier "cmp_in_signal1".

    ** Error: D:/Final Project/Technical/Top/hdl/Rx.vhd(54): (vcom-1484) Unknown formal identifier "cmp_in_signal2".

    ** Error: D:/Final Project/Technical/Top/hdl/Rx.vhd(62): (vcom-1484) Unknown formal identifier "seed_en_out".

    ** Error: D:/Final Project/Technical/Top/hdl/Rx.vhd(70): (vcom-1484) Unknown formal identifier "PN_out2".

    ** Error: D:/Final Project/Technical/Top/hdl/Rx.vhd(78): (vcom-1484) Unknown formal identifier "cmp_out".

    ** Error: D:/Final Project/Technical/Top/hdl/Rx.vhd(80): (vcom-1484) Unknown formal identifier "seed_en_out".

    ** Error: D:/Final Project/Technical/Top/hdl/Rx.vhd(84): VHDL Compiler exiting

    i define all of this names as signals at Rx Entity but still there are errors .

    what should i do about both cases ?

    attached the hdl files project .