Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

close loop at Test Bench

Hi , i want to close loop back at the Test bench between the transmitted data from transmitter to the receiver . both transmitter and receiver implemented at VHDL and they are known to the top ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Hi ,

The last scheme i added was general .

I added now the scheme of my project and code is relevant for this scheme (attached file ) .

The code of : Test Bench , Top, Tx , Rx , PN_Generator , Meta_Fix is also attached at files .

all of them are entities at different files .

The names of I/O ports at visio are the same at code .

The errors at Modelsim are :

1.after compiling testbench :

** Error: D:/Final Project/Technical/Top/simulation/modelsim/TestBench.vhd(49): (vcom-1035) Formal port "ser_in1" has OPEN or no actual associated with it.

2.after compiling top :

** Error: D:/Final Project/Technical/Top/hdl/top.vhd(30): (vcom-1484) Unknown formal identifier "ser_in1".

3.After compiling Rx

** Error: D:/Final Project/Technical/Top/hdl/Rx.vhd(33): (vcom-1484) Unknown formal identifier "ser_in".

When compile the transmitter alone the result were proper serial data at ser_out .