close loop at Test Bench

ok ,

i connect : ser_in1=>ser_in at test bench file and now it compile without errors.

i connect : ser_in => data_in at top file ( ser_in1 is the input port to the top ) .

i declare data_in as a signal at the top file - signal data_in : std_logic; and now top file compile without errors .

At the Rx file ser_in as input port ,

At the Rx file i declare data_in as signal and connect : Data_in=> Data_in_D .

There are 11 errors at Rx file after compiling .

one of the errors is :

1. ** Error: D:/Final Project/Technical/Top/hdl/Rx.vhd(34): (vcom-1136) Unknown identifier "Data_in_D".

Data_in_D is the input port to MetaFix - declared at Rx file . i tried to declare it as a signal at Rx file but still it has the same error .

2. The rest of the errors related to the other signals at Rx Entity/file :

** Error: D:/Final Project/Technical/Top/hdl/Rx.vhd(45): (vcom-1484) Unknown formal identifier "reg_in_signal1".

** Error: D:/Final Project/Technical/Top/hdl/Rx.vhd(53): (vcom-1136) Unknown identifier "cmp_in_Tx".

** Error: D:/Final Project/Technical/Top/hdl/Rx.vhd(54): (vcom-1136) Unknown identifier "cmp_in_Rx".

** Error: D:/Final Project/Technical/Top/hdl/Rx.vhd(53): (vcom-1484) Unknown formal identifier "cmp_in_signal1".

** Error: D:/Final Project/Technical/Top/hdl/Rx.vhd(54): (vcom-1484) Unknown formal identifier "cmp_in_signal2".

** Error: D:/Final Project/Technical/Top/hdl/Rx.vhd(62): (vcom-1484) Unknown formal identifier "seed_en_out".

** Error: D:/Final Project/Technical/Top/hdl/Rx.vhd(70): (vcom-1484) Unknown formal identifier "PN_out2".

** Error: D:/Final Project/Technical/Top/hdl/Rx.vhd(78): (vcom-1484) Unknown formal identifier "cmp_out".

** Error: D:/Final Project/Technical/Top/hdl/Rx.vhd(80): (vcom-1484) Unknown formal identifier "seed_en_out".

** Error: D:/Final Project/Technical/Top/hdl/Rx.vhd(84): VHDL Compiler exiting

i define all of this names as signals at Rx Entity but still there are errors .

what should i do about both cases ?

attached the hdl files project .