clocks from PLL to megafunction sdc

Hi! I'm a beginner in learning of constrains.I'm trying to write sdc-file for sdi megafunction. In UG for that megafunction altera offers the following:

derive_clock_uncertainty
create_clock -name {rx_sd_refclk_135} -period 7.407 -waveform { 0.000 3.703 } 
create_clock -name {rx_sd_refclk_337} -period 2.967 -waveform { 0.000 1.484 } 
create_clock -name {rx_sd_refclk_337_90deg} -period 2.967 -waveform { 0.000 1.484 } 
create_clock -name {tx_sd_refclk_270} -period 3.703 -waveform { 0.000 1.852 } 
create_clock -name {tx_pclk} -period 37.037 -waveform { 0.000 18.519 } 
set_max_delay -from  -to  4.430 
set_min_delay -from  -to  0.000 

In my project I have another situation. Clk 270, 135, 337 and 337 with 90 phase I get from PLLs.

So, my question: how to describe clocks from PLLs to megafunction?

I had tried to write sdc in this form:

#*******************
# Time Information *
#*******************
derive_pll_clocks
derive_clock_uncertainty
set clk_270MHz pll1|altpll_component|auto_generated|pll1|clk
set clk_135MHz pll1|altpll_component|auto_generated|pll1|clk
set clk_337MHz pll2|altpll_component|auto_generated|pll1|clk
set clk_390ph pll2|altpll_component|auto_generated|pll1|clk
#***************
# Create Clock *
#***************
create_clock -name {clk1} -period 50MHz   
create_clock -name {clk2} -period 27MHz 
#*************************
# Create Generated Clock *
#*************************
create_generated_clock -name {c337} -source $clk_337MHz 
create_generated_clock -name {c135} -source $clk_135MHz
create_generated_clock -name {c390} -source $clk_390ph 
create_generated_clock -name {c270} -source $clk_270MHz 
#********************
# Set Maximum Delay *
#********************
set_max_delay -from  -to  4.430
#********************
# Set Minimum Delay *
#********************
set_min_delay -from  -to  0.000   

But quartus sent me warnings 332061 Virtual clock *clk* is never referenced in any input or output dela assigment

Can anyone help me to solve this problem?

May be with example of sdc file with another megafunction, but where clocks are getting from PLL