Forum Discussion

Honored Contributor

7 years ago

clocks from PLL to megafunction sdc

Hi! I'm a beginner in learning of constrains.I'm trying to write sdc-file for sdi megafunction. In UG for that megafunction altera offers the following: derive_clock_uncertainty create_clock ...

Altera_Forum

Honored Contributor

7 years ago

Definitely too much.

create_clock for PLL input clock and derive_pll_clocks will already define all PLL output clocks.

Suggest to review the excellent TimeQuest user guide in Altera Wiki. http://www.alterawiki.com/wiki/timequest_user_guide

Forum Discussion

clocks from PLL to megafunction sdc

Recent Discussions

Timing analysis - long combinational path

QuartusPro 25.3 Crashed after using the Signal Tap Logic Analyzer

Duplicate_hierarchy_depth / duplicate_register

Automatically added negative node for TDS output doesn't work with Agilex 5

Quartus 20.1std compilation fails for Quartus map - Device 10AS057K2F40I1SG