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Altera_Forum's avatar
Altera_Forum
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16 years ago

Clocks for synchronization chain

Hi all,

This is a different question but related to my earlier thread. I have implemented a simple synchronous sequential logic, couple of gates and two FF. Input to the logic are two asynchronous external signals. To reduce metastability, I have added a synchronization chain for both signals referring to Understanding metastability in FPGA-wp-01082-quartus-ii-metastability.pdf.

My first question refers to Fig. 3, page 3. The figure shows two separate clocks: Clock 1 and Clock 2 for the synchronizing chain -why two clocks? Any clock inside the FPGA is eventually derived from system clock. And is timeclock1 less than or greater than timeclock2.

Second question is regarding MBFT data. what is the best way calculate it? do i have to use the actual input signals? Is there some documentation simpler than Managing Metastability with the Quartus II Software-qts_qii51018.pdf?

Thanks

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    why two clocks

    --- Quote End ---

    You didn't read the paper thoroughly. clk1 is simply representing the other clock domain. It's not belonging to the synchronizer.

    As a side remark. The common problem with processing of asynchronous external signals is not metastability. It's to completely omit synchronizing and feed the signal directly to multiple registers.

    In a simple example: 

    IF external_signal = '1' THEN
  next_state = triggered;
END IF;

    next_state is fed to a number of registers representing the state variable. Each register is sampling independently a combinational input depending among others on external_signal. If the edge of external_signal coincides with the clock edge, the state variable can be set to a wrong or even illegal state. This problem hasn't to do with metastability, it's a simple case of missing synchronization.

    Providing a single synchronizing register removes nearly all of the above problems. The metastability discussion is about those cases, where a single register isn't enough.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    @ FvM

    Thanks for the reply. As you said above, it is essential to synchronize external asynchronous inputs with the internal logic. Also, reading from your reply, I am assuming that MBFT data is not important, since metastability is not the major issue. Thanks for making that clear.