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why two clocks
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You didn't read the paper thoroughly. clk1 is simply representing the other clock domain. It's not belonging to the synchronizer.
As a side remark. The common problem with processing of asynchronous external signals is
not metastability. It's to completely omit synchronizing and feed the signal directly to multiple registers.
In a simple example:
IF external_signal = '1' THEN
next_state = triggered;
END IF;
next_state is fed to a number of registers representing the state variable. Each register is sampling independently a combinational input depending among others on external_signal. If the edge of external_signal coincides with the clock edge, the state variable can be set to a wrong or even illegal state. This problem hasn't to do with metastability, it's a simple case of missing synchronization.
Providing a single synchronizing register removes nearly all of the above problems. The metastability discussion is about those cases, where a single register isn't enough.
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