Clocking Block not working correctly?
Hello,
I am having a problem and want to make sure its not user error before chalking it up to a bug.
I am designing a testbench and checking the status of a set of signals that are contained in an interface using a class and accessed by a method in that class. That interface contains a clocking block that is used to access them.
My interface looks like this:
interface interface_name ( input logic clk, input logic in0, in1, in2, in3; ); default clocking cb @(posedge clk); input in0; input in1; input in2; input in3; endclocking endinterface
When I simulate in Questa Intel FPGA Edition, I get the following screenshot. The clock is at the top. Followed by one of the non-clocked interface signals. The very bottom signal is the same signal inside of the clocking block.
The cursor shows where the posedge of the clock is and where the error occurs. The input sampling of the clocking block should mean that the value of the signal is sampled in the preponed region of that time slot. That value (1) should be used for any following statements executed in that time slot but the old value (0) is still being used.
The code that uses the clock blocking signals looks like this:
@ (posedge clk); if (interface_name.cb.in0 == '0) return '0; else return '1;
The above code is executing the if branch instead of the else branch.
Am I not understanding something?