Clocking Block not working correctly?

Assuming I understand correctly what you are doing, in your code snippet, you're using the clocking block signal interface_name.cb.in0 inside the @ (posedge clk) block. However, the clocking block signal is not guaranteed to have its value updated until the end of the clocking block. This means that if you're using the signal inside the @ (posedge clk) block, you may be getting the old value of the signal.

You can move the signal access outside of the clocking block and into a separate always block that triggers on the clock edge. For example:

always @(posedge clk) begin

if (interface_name.in0 == 1'b0) begin

// Do something if in0 is low

end else begin

// Do something else if in0 is high

end

end

By doing this, you're ensuring that you're sampling the signal at the correct time (on the clock edge) and not relying on the timing of the clocking block.