Clock to output delay tco for DFF

Hi,

Thanks for the reply. Sorry for my late reply, I forgot to check this thread for some time. I did not explain my original problem correctly. I had previously implemented a sequential logic network using discrete FF and AND gates. I was trying to port the same design on a CPLD.

The particular senario I am worried about is: I have two input signals which are generated by an external circuit. These signals are checked against a specific state transition inside the CPLD. The problem occurs when both input signals are transitioning from 0 to 1 (or 1 to 0) at the same time as the CPLD clock rising edge. One of the FF then will go into a metastable state and my output does not follow the state logic. But I found that if there is a FIXED delay between the input and output of the FF, the final logic output will not be affected, even if DFF goes metastable. Hence my question about tco of DFF.

The FF clock is multiple of system clock, generated by a counter.

I solved my original problem by putting sychronizing FF at the beginning of my logic to make sure the input signals are now adjusted to CPLD clock instead of the external clock, so clock transitions and input signal transitions don't occur at the same time (hopefully).