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Hi all,
I have implemented a simple synchronous sequential logic, couple of gates and two FF. Quartus II by default uses Classic Timing Analyzer which shows a delay of ~4ns from clock input to data output for the D flip flop that is used to store state information. I don't know if this is min or max delay, and even if it is the guaranteed tco for the D flip flop. The tco I want is NOT device pin input to pin output, but the input to output of a DFF inside the CPLD. I/O Output Timing for Altera Devices-an366.pdf does not give this specific info. And I don't know how to setup Timing Analyzer (atleast not yet, trying to learn.) As an aside, this information is specified for discrete 14-pin DFF devices.
My experience level is beginner, I don't know any HDL, but I understand digital logic and use BDF to implement all logic. Target hardware is Max II EPM240, system clock is 10ns. Flip flop clock is 80ns.
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Hi quintus,
why to want to know the tco of the registers inside the FPGA ? Quartus handles the internal timing for as long as you have set your design constraints.
BTW: How do you generate the Flip Flop clock ?
Kind regards
GPK
Honored Contributor
