clock skew vs clock latency

Hi Kaz,

Sorry for the confusion. I didn't write down the complete set_input_delay syntax in the post. Yes, there is an input port associated with it in my actual SDC.

My focus here is to discuss the use of two methods, so I omitted the target of set_input_delay, assuming we all know it is applied to an input port.

Hi rbugalho,

That is exactly my point. I think these two methods are equivalent only when we use them in timing verification. But when we use them as timing constraints to direct Quartus to compile a design, they are different. Because Quartus generates different timing netlists with these two methods.

As for the random seed, I think you are talking about the value we can put in under Fitter Settings tab,right? But normally we don't need to change that number, unless the compilation can't meet the timing requirement no matter how we tweak our constraints and source codes, so we need to give a try with another seed number.

With the same constraints and the same source code, we should always get the same result on successive compilations. The result is repeatable. I think I verified this with experiments.