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Altera_Forum's avatar
Altera_Forum
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16 years ago

Clock Skew Problem

Hi, I read this forum lots - post very little. Time and time again I hear talk about using clock enables to avoid messages about clock skew. I am writing in Verilog and would like an example of...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Ignore what I just wrote about the counter[6] == 1'b1. That will have the enable high for 64 clocks in a row, which is wrong. Sanmao had it write that the enable pulses for once clock cycle, i.e. enables the register for a single clock and then disables it for 127, so you're seeing 1/128 edges.

The .sdc stuff is correct though.