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Altera_Forum's avatar
Altera_Forum
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16 years ago

Clock Skew Problem

Hi,

I read this forum lots - post very little. Time and time again I hear talk about using clock enables to avoid messages about clock skew. I am writing in Verilog and would like an example of how to divdee by 2, divide by 16, and maybe divide by 128 using clock enables. With so many folks who know what is up on here, I am humbly hoping for some help.

Also, is it true that if the division is done in this way, the divided output will be only one input clock cycle wide?

Thanks,

Tony

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    There are several ways in which this clock enabling can be done in Verilog.

    In the code snippet below you can find two processes. The first process generates a clock_enable pulse every 128 clock cycles. It is easy to update this code to other cycle lengths.

    The second process uses the clock_enable signal to have something executed every 128 clock cycles. 

    reg clock_enable;
reg  counter;
 
always @(posedge clock)
  if (reset) begin
    clock_enable = 0;
    counter = 0;
  end else begin
    if (counter == 7'b1111111) begin
     counter = 0;
     clock_enable = 1;
    end else begin
      counter = counter + 1;
      clock_enable = 0;
    end
  end
 
always @(posedge clock)
  if (reset) begin
    // ... bla bla bla;
  end else begin
    if (clock_enable) begin 
    // do whatever needs to be done every 128 clock cycles
    end
  end
    Verilog designers could be very well tempted to use a clock enable signal as generated above in the sensitivity list of the always @(posedge clock)-construct. This is however bad design practice, as you are also menitoning in your question. When doing this your design will be vulnerable to glitches, races and hazards, and you will probably not design robust hardware.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Note that it doesn' t have to be 1 pulse signal. Just chane the if condition to:

    if (counter[6] == 1'b1) begin

    It will now be low for 64 clocks, high for 64 clocks, etc. And as mentioned, it should not be part of your sensitivity list, just part of the synchronous logic after the clock.

    The coding is generally pretty straightforward, but the timing analysis gets difficult. Note that everything will be timed to the clock rate, which is too fast. I believe there are posts on this board and the website about use get_fanouts, which is what you'll want in your .sdc file.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Ignore what I just wrote about the counter[6] == 1'b1. That will have the enable high for 64 clocks in a row, which is wrong. Sanmao had it write that the enable pulses for once clock cycle, i.e. enables the register for a single clock and then disables it for 127, so you're seeing 1/128 edges.

    The .sdc stuff is correct though.