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Altera_Forum's avatar
Altera_Forum
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14 years ago

Clock skew from using global and local routing

I'm chasing a number of hold and sometimes setup violations that stem from impractical amounts of clock skew. When I pull up a failing path in the technology viewer, I find that one of the flops is ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Adding an lcell seems to help for the pin driven clocks but I also have some clocks are gated that have the same problem and the lcell in not effective. To be clear, I'm referring to flops on the same side of the clock gate. For some flops, the clock path is gate -> regional or global buffer -> flop. Others are gate -> (data network) -> flop.

Auto global is turned on. There are no global buffers defined in the RTL for this clock.