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i think i found some clues. The launch and latch clocks are out of phase by 90 deg but derived from same pll. I am wondering if clock delay will show up in such a case i.e. if the launch and latch clocks are not exactly the same. I am not passing timing, i get -ns as i mentioned earlier. But fitter does say the first clock was compensated.
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It is not clear from your post what is your launch clock and what is your latch clock. I assumed so far you are looking at external data coming in with its clock being fed into PLL then pll clockout used as latch for same data at io registers. Then timing will depend on your set_input_delay value which tells the tool the relation of your incoming data to its clock at pins. It will help to have brief account of your clocking and data failure section.
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