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Altera_Forum's avatar
Altera_Forum
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13 years ago

clock path delay

Hi, I am generating my internal clock from a pll in normal compensating mode. pll is fed by board clock and pll is just used for compensating (i.e. mult = 1, div = 1) I am seeing this in my s...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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I see. I just tried some work on PLL and it turned out that the tool does not actually report physical delay but it reports delay after compensation so you should not get 3.9 ns (I got about 0.3 ns in compensation mode but 3.2 ns without compensation and was reported as such).

Now the question is back why do you get 3.9 ns? are you looking at right path? Do you actually pass timing after setting set_input_delay and how much slack do you get?

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i think i found some clues. The launch and latch clocks are out of phase by 90 deg but derived from same pll. I am wondering if clock delay will show up in such a case i.e. if the launch and latch clocks are not exactly the same. I am not passing timing, i get -ns as i mentioned earlier. But fitter does say the first clock was compensated.