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I add my vote to that of rbugalho that delay is compensated through clock phase. physical delay will still be reported because clkin to pll takes time and clkout to register takes time and the pll can't pass clk in zero time but makes it appear with minimum delay through phase i.e. your clkout should reach the register as if there was no delay. After all do timing and see if you have problems in which case you can manually change the pll phase.
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@kaz, thanks.
my problem is that: data-arrival reported by timequest is clock-path-delay+data-path-delay = 3.9 + 7 = 10.9
clock period itself is 7.5, so data path by itself is meeting setup. But the additional clock path delay is now causing the violation.
clock path delay shouldn't be there in the arrival report (or it should be reported the same in arrival and required) if its compensated.
how should i find out more bout this
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