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Hi, I am sorry, I am totally confused. If pll is compensating for clock network skew, then the delay shouldn't show up in the setup, isn't it.
What I am seeing in the report is that data_arrival = clock_delay + data_delay.
And clock_delay is over 3.9ns as noted above (which means my internal clock can never be fast in this case)
I am trying to reconcile my understanding with the following statement in the clocks and plls document: "In normal mode, the delay introduced by the GCLK or RCLK network is fullycompensated. Figure 5–25 shows an example waveform of the PLL clocks’ phase relationship in normal mode" I double checked that the PLL_B1 is fed by dedicated clock in, so it
should be fully compensated. So almost all of the time between launch clock edge and latch edge should be available for data delay.
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I add my vote to that of rbugalho that delay is compensated through clock phase. physical delay will still be reported because clkin to pll takes time and clkout to register takes time and the pll can't pass clk in zero time but makes it appear with minimum delay through phase i.e. your clkout should reach the register as if there was no delay. After all do timing and see if you have problems in which case you can manually change the pll phase.
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