clock-domain-crossing timing simulation

I am talking about timing simulation. I want to do SDF-simulation of a routed design that has a async FF (asymc means that data-in may violate setup/hold requirements). I've taken care of metastability by using a two-stage FF synchronization, the problem is that during timing simulation if setup/hold is violated then the output of the first-stage FF will go to "X". Of course at the next clock cycle it will get a valid value; but in the meantime the "X" will propagate into the other clock domain.

I used to have this problem at a Xilinx project as well; the solution was to apply an ASYNC_REG attribute on these FFs. This attribute instructs the Xilinx tools to instantiate a special FF in the generated post-route simulation netlist. Actually the instantiated FF was a standard FF but with the generic XON set to false. This generic causes the FF to drive its output to its previous value if a violation occurs.

I checked the respective Altera library component (called stratixii_lcell_ff) which has also such a generic that presumably does the same thing. I can solve the problem by manually altering the generated VHDL file but would like to avoid that.

The solution would be to find a way to instruct Quartus to use FF with XON set to false for these particular registers.

Sorry for the lengthy explanation.