Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Clock division with DFF

Hi,

I am using Quartus 13.0SP1 to program an EPM7128S

I am trying to divide a clock using DFFs, the DFF block didn't seem to give me a 50:50 duty cycle, so I am trying DFF2 as shown.

When I simulate the circuit, some of the outputs are tristated, can anyone tell me where I am going wrong please?

(PHI/3 or the disconnected block shown are not relevant for this question)

regards

Dave

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Using logic to divide a clock will never give you a great signal as it will be affected by skew. You should use a PLL to get a proper clock.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Thanks for the reply, the EPM7128S does not have PLLs

    I take your point about skew, but is there any reason that cascades DFFs (or DFF2s) should not divide as I expect them to?

    regards

    Dave