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Altera_Forum
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9 years ago

Clock division with DFF

Hi, I am using Quartus 13.0SP1 to program an EPM7128S I am trying to divide a clock using DFFs, the DFF block didn't seem to give me a 50:50 duty cycle, so I am trying DFF2 as shown. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Using logic to divide a clock will never give you a great signal as it will be affected by skew. You should use a PLL to get a proper clock.