clock division in verilog

I'd like some help to understand why this code didn't work.

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module emissao2(

clk,

enable_in,

over_temp_in,

MSB_in,

LSB_in,

enable_led,

over_temp_led,

MSB_led,

LSB_led,

enable_out,

over_temp_out,

MSB_out,

LSB_out,

ctrl_p_1,

ctrl_n_1,

ctrl_p_2,

ctrl_n_2,

ctrl_p_3,

ctrl_n_3,

ctrl_p_4,

ctrl_n_4);

//---Input Ports---

input clk;

input enable_in;

input over_temp_in;

input MSB_in;

input LSB_in;

//---Output Ports---

output enable_led;

output over_temp_led;

output MSB_led;

output LSB_led;

output enable_out;

output over_temp_out;

output MSB_out;

output LSB_out;

output ctrl_p_1;

output ctrl_n_1;

output ctrl_p_2;

output ctrl_n_2;

output ctrl_p_3;

output ctrl_n_3;

output ctrl_p_4;

output ctrl_n_4;

//---Input Ports Data Type---

wire clk;

wire enable_in;

wire over_temp_in;

wire MSB_in;

wire LSB_in;

//---Output Ports Data Type---

reg enable_led;

reg over_temp_led;

reg MSB_led;

reg LSB_led;

reg enable_out;

reg over_temp_out;

reg MSB_out;

reg LSB_out;

reg ctrl_p_1;

reg ctrl_n_1;

reg ctrl_p_2;

reg ctrl_n_2;

reg ctrl_p_3;

reg ctrl_n_3;

reg ctrl_p_4;

reg ctrl_n_4;

reg [3:0]count;

initial begin

count = 4'd0;

ctrl_p_1 = 1'b0;

end

always @(posedge clk)

begin

if(count==4'd10)

begin

count<=3'd0;

ctrl_p_1 <= ~ctrl_p_1;

end

else

begin

count<=count+1;

end

end

endmodule

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It compile but does not work. I made the assignments correctly, and i will use all this ports, this is just a inicial code just to see if works.

I'm using Quartus II 13.0, to program Altera DE2 (EP2C35F672C)