clock division in verilog

You missed to say what "didn't work" in your code. In the present code, ctrl_p_1 will be toggled after each 10 clock cycles.

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Initial blocks are not synthesizable. Change it to a reset condition of your always @(posedge clock)

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They are synthesized as initialization during power on reset. Initializing to 0 is redundant, because this is the default register state without additional initializations. A reset condition can be repeated at will, in contrast to POR which is only performed once.