Clock divider

Hi all

Again with VHDL problems :p

I need a clock divider to run a Z80.

My board fréquency is 50Mhz and I need 3,57Mhz.

I found this code but it doesn't seem working with all "constant CLK_SLOW_FREQ"

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use ieee.numeric_std.all;

use ieee.math_real.all;

entity CPU_CLOCK is

port (CLKIN : in std_logic;

CLKOUT : out std_logic );

end entity CPU_CLOCK;

architecture arch of CPU_CLOCK is

constant CLK_MASTER_FREQ: natural := 50000000;

constant CLK_SLOW_FREQ: natural := 3570000;

constant MAX_COUNT: natural := CLK_MASTER_FREQ/CLK_SLOW_FREQ;

shared variable counter: natural := 0;

begin

clock_proc: process(CLKIN)

begin

if rising_edge(CLKIN) then

counter := counter + 1;

if (counter >= MAX_COUNT) then

counter := 0;

CLKOUT <= '1';

else

CLKOUT <= '0';

end if;

end process;

end arch;

Altera_Forum
Honored Contributor
12 years ago
After playing a bit with ALTPLL I can get 10.71Mhz :50/14*3

After that I can get 3.57Mhz : 10.71/3

:cool:
Altera_Forum
Honored Contributor
12 years ago
Hi Bertulus, can you explain why in FPGA, using clock enable is better? Thank you.
Altera_Forum
Honored Contributor
12 years ago
Clock enable should be used in synchronous circuits. In this circuits all flip-flop receives the same clock signal, so in the moment active edge occurs all flip-flop sample its inputs and copy to outputs AT THE SAME TIME. This way, it easy to predict circuit behavior and know the maximum operation frequency:

fmax = 1 / ( Tcq + Tsetup + TnextMAX )

In this synchronous circuit you can't make a gated clock in vhdl or divided with a FF chain ( connected one output to the clock of the next one ) because different FF not receive same clock. The only way to slow down the frequency of counter is to freeze the counter using a MUX. You copy the output of the counter register to its input so the counter are stopped. When the clock enable is on, the mux connect the input to an incremented version of the output, so the counter counts, but only for a clock period. The overall result is that counter increment one time in N clock cycles ( slow down ).

If you don't use synchronous technique ( i did it on a fpga, that I don't undestand is how Quartus and Cyclone I did it ) there will be a lot of timing issues.

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