Clock divider

Clock enable should be used in synchronous circuits. In this circuits all flip-flop receives the same clock signal, so in the moment active edge occurs all flip-flop sample its inputs and copy to outputs AT THE SAME TIME. This way, it easy to predict circuit behavior and know the maximum operation frequency:

fmax = 1 / ( Tcq + Tsetup + TnextMAX )

In this synchronous circuit you can't make a gated clock in vhdl or divided with a FF chain ( connected one output to the clock of the next one ) because different FF not receive same clock. The only way to slow down the frequency of counter is to freeze the counter using a MUX. You copy the output of the counter register to its input so the counter are stopped. When the clock enable is on, the mux connect the input to an incremented version of the output, so the counter counts, but only for a clock period. The overall result is that counter increment one time in N clock cycles ( slow down ).

If you don't use synchronous technique ( i did it on a fpga, that I don't undestand is how Quartus and Cyclone I did it ) there will be a lot of timing issues.