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OrF's avatar
OrF
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

CLK-30028 - Invalid Generated Clock

Hi I'm trying to define generated clock out of the pll. and I get the following violation notification "CLK-30028: Invalid Generated Clock" https://www.intel.la/content/www/xl/es/programmable/quar...
Timing
OrF's avatar
OrF
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

sorry I didn't understand your answer.

1.what is "cuccssgully" ? successfully ?

2. I do not use "derive_pll_clocks" (drive_pll??) - since it is Stx10.

3. I still do not understand why the STA does not calculate the clock latency from its input to output clock.