Forum Discussion
Occasional ContributorCLK-30028 - Invalid Generated Clock
Super Contributorderive_pll_clocks is supported with the newer devices, you just don't need to explicitly put it in your .sdc file anymore. The generated clock constraints are automatically created.
Contributor@sstrell, that doesn't appear to be the case. Have you tried it? I just tried it again to confirm. Quartus is definitely not automatically creating generated clock constraints for PLL clocks from a hand-instantiated IOPLL atom in Stratix 10 or Agilex. Without user-added create_generated_clock constraints, the PLL clocks remain unconstrained.
This can be confirmed in multiple places:
- During the flow, Quartus rightly issues "Warning (332060): .... <name> was determined to be a clock but was found without an associated clock assignment" for each used PLL clock.
- During the flow, the PLL clocks don't show up in the "Info (332111)" tables that list the constrained clocks found in the design and their periods.
- In the STA report, in the "Clocks" table, the PLL clocks don't show up.
- In the STA report, in the "Unconstrained Paths Summary" table, you can see them counted in the "Unconstrained Clocks" count.
- In the STA report, in the "Clock Status Summary" table, they explicitly show up with Status "Unconstrained" .
- In the STA report, paths in these clock domains aren't analyzed.
- Etc.
- sstrell
I've never not used the IP Parameter Editor for a PLL, so I don't doubt you.
- roeekalinsky
If you're curious: With the IP Parameter Editor, have a look at the SDC file and related TCL scripts that it generates. That's where your create_generated_clocks constraints are coming from.
