CLK-30028 - Invalid Generated Clock

Quartus doesn't even support derive_pll_clocks with Stratix 10 and Agilex. Quartus supports derive_pll_clocks for Arria 10, Cyclone 10 GX, and earlier device families. But for some perplexing reason Intel/Altera decided not to support it starting with Stratix 10.

Where derive_pll_clocks is supported, it is certainly the preferred method for constraining PLL output clocks, being the simplest method for the user and the least error prone. It looks at the configuration of each PLL instance and automatically translates that to the correct create_generated_clock constraints. No good reason not to use it, if supported. But for Stratix 10 and Agilex it's not supported, so that's moot.

In the absence of derive_pll_clocks, you do need create_generated_clock constraints for the PLL output clocks.

If you instantiate your IOPLL via wizard-generated IP, then the IP will include the necessary constraints.

If you manually instantiate your IOPLL atom without making use of the wizard-generated IP, then you do need to also manually add the appropriate create_generated_clock constraints. And make sure they're correct for your PLL configuration! Quartus won't necessarily complain if they don't match the PLL configuration, and then your static timing analysis will just be wrong.