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OrF's avatar
OrF
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

CLK-30028 - Invalid Generated Clock

Hi I'm trying to define generated clock out of the pll. and I get the following violation notification "CLK-30028: Invalid Generated Clock" https://www.intel.la/content/www/xl/es/programmable/quar...
Timing
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
2 years ago

I'm not sure why the Design Assistant is calling this out, but since you're using a 3rd-party tool, you should issue a write_sdc command (or choose the option in the Timing Analyzer) to write out a full .sdc file for use by the other tool that will include the correct create_generated_clock constraints.

Other than that, if your timing analysis is accurate and you are closing timing, I'd ignore the DA.

OrF's avatar
OrF
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

the 3rd-party tool is for the Synthesis Part not for the P&R and timing closure . therefore I dont see the point to provide the sdc to the 3rd-party tool , even though I did generated the sdc, and looking at it I didn't find any additional constraints .

this issues DOES effect the timing calculation since it doesn't take into account the the timing delay from the input of the pll to the output of the pll.