Forum Discussion
Occasional ContributorCLK-30028 - Invalid Generated Clock
Super ContributorWhat is your target device and why do you not want to use derive_pll_clocks (which is applied automatically in recent devices anyway)?
Does your clock report show the PLL output clock(s) correctly and what you expect?
Occasional Contributor1.My Target device is Stratix 10M .
2. Yes the Clocks are correct . in the report.
3. the reason I'm not using since I'm using derive_pll_clocks Synplify Premier for the synthesis stage .
- FvMA pll clock is no generated clock, thus the error.
- OrF
As far as I see , and know output clock of pll is a generated clock.
"You apply generated clocks most commonly on the outputs of PLLs"
https://www.intel.com/content/www/us/en/docs/programmable/683068/18-1/deriving-pll-clocks.html
"The Derive PLL Clocks (derive_pll_clocks) constraint automatically creates clocks for each output of any PLL in your design. derive_pll_clocks detects your current PLL settings and automatically creates generated clocks on the outputs of every PLL by calling the create_generated_clock command."
