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Altera_Forum's avatar
Altera_Forum
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14 years ago

CIII+ddr

I've some problems with DDR memory:

my system:

*own PCB

*CycloneIII (EP3C40F484)

*DDR (Micron mt46v16m16p-6t)

I'm trying to test memory with software template test_mem

In SopcBuilder I generated: h**p://pic.2x4.ru/image-CE62_4D52559A.jpg

(sorry can't post pics yet)

Add all *.sdc generated by SopcBuilder into my project.

In my own SDC there is only "derive_pll_clocks".

TimeQuest shows no problems.

But when I start debugging, it "freezes" just after downloading software into device.

--- Quote Start ---

Downloading 02020000 ( 0%)

Downloaded 28KB in 0.6s (46.6KB/s)

Verifying 02020000 ( 0%)

Verified OK

Leaving target processor paused

--- Quote End ---

The code and reset vector are both located in onchip memory.

There are some critical warnings from fitter in Quartus: h**p://electronix.ru/forum/index.php?act=attach&type=post&id=54496

I can do nothing with them. I've tried to locate this ..input_cell_h[0] by assignment, but warning dissapeared again with new unreached destination. Anyway I studied out that altmemphy calibration is faild.

The internal ctl_cal_fail goes high after global_reset_n deassertion.

Actually I'me not sure that there are no problems in PCB Layout.

PS: strange info in

"MegaCore IP Library Release Notes and Errata"

on page 64:

sopc builder not supported for ddr sdram controller with altmemphy

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    HI ,

    It may happen that it is not supported.I am also working with DDR2 memory with CIII.

    I was also getting the error Leaving target processor paused.But f you leave it for some time it will run.Try in the debug mode first.

    I dont find any problem but if you can give more info about where are the problems?
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hi,

    There were mistakes in the TOP of my FPGA project, some pins were floating. When I corrected it, nios started to work fine and the RAM passed all tests. So it works now on 100MHz (133Mhz are declared as maximum for my configuration, but i've not tried yet).

    The only thing i haven't won yet is warnings (I posted link upper).

    For other DDR pins location the wornings disappear. So I'll correct the pinout in next PCB revision.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hey

    How did you correct the floating pins.I also have them in my design.Did you put them to ground?
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    no I mean one of DDR signals. It hadn't reached DDR pin.

    It was a stupid mistake. :)

    Floating pins that U mean I usually laeve as tristate input.

    On PCB they are not connected.

    As I know it's not good, but I've never got problems with them.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I would like to know, if it is possible, which voltage regulator you've used in the design. I 've read that is neccessary a ddr voltage regulator to work properly instead of using a typical lmXXX regulator.

    Thanks

    ifdm
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I used EN5322QI.

    The pwr was shared for DDR and FPGA.

    It doesn't care linear or pulse, i think.

    The current is important.