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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

CIC filter in VHDL

Hello all,

As in title, I want to realize CIC filter written in VHDL.

- specifications of CIC filter

> clock : 50 MHz

> decimation rate : 500

> output freq. : 100 kHz

> output word width : 12 bit

So the point is that since I got 500th order of multiplierless FIR filter (with transfer function H(z) = Sigma((i=0..499), (z^-i))) for I need decimation rate of 500

but I am pretty sure this is too big...

I want to know how to realize this CIC filter with much less hardwares (e.g. adders, flipflops...).

Any helps will be appreciated.

Yukihiro Hatagishi

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Try cascading some filters. Implement a 5x decimation then two 10x decimations.

    5 gets you to 10MHz then at the 10MHz rate implement a 10x decimation filter to get you down to 1MHz then at the 1MHz rate implement another 10x decimation filter to get you down to 100 kHz. This is a simple example and there are many ways of doing this depending on your application, so I suggest finding a good book on multi-rate signal processing.