CIC Filter: code not compiling!

Hi,

could someone please take a look at the code below and tell me why it is not compiling?

module cicdecim64 (
input            clk, 
input             reset,
output reg        clk2,
input signed        x_in,
output signed         y_out);
parameter hold=0, sample=1;
reg            state;     //sample or hold states
reg            count;            //count till 63 starting from 0
reg signed        x;                    //input
wire signed        sx;                //sign extended input
reg signed         i0;                //Integrator output section 0
reg signed        i1;                //output section 1 under the consideration of Haugenauer's pruning
reg signed        i2;
reg signed         z0, c1, c0;     // Integrator+COMB 0
reg signed         z1, c2;
reg signed         z2, c3;
assign sx={{18{x_in}},x_in};
always @(posedge clk or posedge reset)
  begin : FSM
    if (reset) begin       // Asynchronous reset
     x<=0;
     i0<=0;
     i1<=0;
     i2<=0;
     c0<=0;
     c1<=0;
     c2<=0;
     c3<=0;
     z0<=0;
     z1<=0;
     z2<=0;
      count <= 0; 
      state <= hold;
      clk2  <= 0; 
    end
     else begin 
      if (count == 31) begin
          count <= 0;
          state <= sample;
          clk2  <= 1; 
      end
        else begin
        count <= count + 1;
        state <= hold;
        clk2  <= 0;
      end
    end
x <= sx;
i0 <= i0 + x;                         
i1 <= i1+i0;
i2 <= i2+i1;
if((count>16)&&(count<32)) // ERROR HERE
clk2 <=1;
else
clk2 <=0;
// COMB
if(state==sample) // ERROR HERE
begin
count <= 0;
c0 <= i2;
z0 <= c0;
c1 <= c0-z0;
z1 <= c1;
c2 <= c1-z1;
z2 <= c2;
c3 <= c2-z2;
end
end
assign y_out=c3;//Gain compensation
endmodule

I keep on getting the following error:

Error (10200): Verilog HDL Conditional Statement error at wb_hp_f.v(59): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct

Error (10200): Verilog HDL Conditional Statement error at wb_hp_f.v(66): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct

Additional tips are also welcome.

Thanks in advance