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Altera_Forum
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13 years ago

CIC Filter: code not compiling!

Hi, could someone please take a look at the code below and tell me why it is not compiling? module cicdecim64 ( input clk, input reset, output reg clk2, i...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Disclaimer: I am not great with Verilog.

Take a look at line 55 ( x <= sx; ). Should this (and the 7 lines below it) be happening on posedge clk? If yes, you have an end (on line 53) in the wrong place. If no, I'm not sure you can use the "if" construct. Take a second look and see if anything pops out at you.

I hope this helps.