CIC Filter: code not compiling!

Hey FvM,

That makes sense. I changed the code to the following:

module cicdecim64 (
input			clk, 
input 			reset,
output reg		clk2,
input signed		x_in,
output signed 		y_out);
parameter hold=0, sample=1;
reg			state; 	
reg			count;			
reg signed		x;					
wire signed		sx;				
reg signed	 	i0;				
reg signed		i1;				
reg signed		i2;
reg signed	 	z0=0;
reg signed	 	c1=0;
reg signed	 	c0=0;
reg signed	 	z1=0;
reg signed	 	z2=0; 	
reg signed	 	c2=0;
reg signed	 	c3=0;
always @(negedge clk)
begin: FSM
case(state)
hold: begin
if(count<63)
state <= hold;
else
state <= sample;
end
default:
state <= hold;
endcase
end
assign sx={{18{x_in}},x_in};
always @(posedge clk or posedge reset)
  begin 
    if (reset) begin  	 // Asynchronous reset
	 x<=0;
	 i0<=0;
	 i1<=0;
	 i2<=0;
	 //c0<=0;
	 //c1<=0;
	 //c2<=0;
	 //c3<=0;
	 //z0<=0;
	 //z1<=0;
	 //z2<=0;
      count <= 0; 
     
      clk2  <= 0; 
    end
	 else begin 
x <= sx;
i0 <= i0 + x; 						
i1 <= i1+i0;
i2 <= i2+i1;
case(state)
sample: begin
c0<= i2;
count<=0;
end
default:
count<=count+1;
endcase
if((count>16)&&(count<32))
begin
clk2 <=1;
end
else begin
clk2 <=0;
end
end
end
// COMB
always @(posedge clk2)
begin
z0 <= c0;
c1 <= c0-z0;
z1 <= c1;
c2 <= c1-z1;
z2 <= c2;
c3 <= c2-z2;
end
assign y_out=c3;//Gain compensation
endmodule

It synthesizes now, but I'm concerned about the reset process. I cannot add the reg driven by clk2 in the 1st reset, and if I include a second reset in the always @(posedge clk2) block, it will endup conflicting with the fact that c0 has been used previously in the block driven by the original clk (when state=sample). How to solve this?