CIC and FIR megacores

Question

Dear Forum

I have designed a narrowband LPF using matlab which comprises a 12 stage CIC decimating filter with a decimation rate of 495. This is followed by a 361 tap Compensating FIR. This combination (with the right FIR coefficients) results in the right frequency response... so next is to build it in Quartus.

I thought it would be a simple case of just adding a CIC megacore, and connecting it to a FIR megacore (both with the appropriate settings). However, it seems a little more complicated than that.

Has anyone any ideas on how the two megacores should be connected and if other intermediate blocks are needed? Does the FIR, for example, have to have a different clk input (because of the decimation in the CIC)?

The Stratix III I'm going to use is running at 93.333MHz, and I the final output signal is supposed to be at this rate (does this mean an interpolater needs to be added, or does the CFIR deal with that?).

Any, I can't find any examples that both utilize a CIC and a C-FIR, although I can find plenty about the theory, and how to calculate the FIR coeffs.

Many thanks, Kurt

altera_forum · Answer

If the input sample rate is 93 MHz, than the CIC output rate is 93/495 = 188 kHz. If the FIR filter is following the CIC, it's supposed to work at 188 kHz sampling rate, that's the purpose of a decimation filter.

altera_forum · Answer

Thanks FvM,

I kinda thought that was the case - what threw me was the fact that the matlab generated script (when one instantiates the CIC megacore) asks for the sampling rate BEFORE the CIC. This made me wonder if the compensation filter also compensates (i.e., interpolates) for the decimation as well as the passband droop... it is odd that given a compensation filter goes hand in hand with a CIC in many instances, why none of the Altera examples provide a project that concatenates a CIC with a FIR, other than in theoretical terms.

So given the CIC takes us into a different clock domain, does the OUT_VALID output signal from the CIC megacore become the CLK input signal for the (compensation) FIR megacore?

AND presumably I'd need to add an Interpolating CIC to get back to the 93.333MHz domain, yes?

Kind regards, Kurt

altera_forum · Answer

OR, does the OUT_VALID from the CIC go into the AST_SOURCE_READY of the FIR and everything stays at 93.333MHz?

altera_forum · Answer

Yes, you can operate the FIR filter in the same clock domain as the CIC, just the dataflow has to be synchronized.

I don't understand however your considerations about interpolating the CIC output back to 93 MHz. If a CIC is used for decimation, why you should undo the operation?

Generally, you can find various multi-stage decimator or decimating filter designs in literature. The main point is to understand their operation in terms of digital signal processing, particularly the multi-rate aspect. Then the translation to a FPGA design shouldn't be an issue.

I assume, that the sampling rates can also be clearly identified in your MatLab prototype.

altera_forum · Answer

there are reasons to use a multirate filter and have the output at the original sample rate. for example, narrow band filters in an audio system where the CODEC runs at a single sample rate.

there are usually significant savings in resources when downsampling then upsampling (rather than doing all filtering at the original sample rate) unless your decimation factor is only 2.

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CIC and FIR megacores

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