CIC and FIR megacores

Yes, you can operate the FIR filter in the same clock domain as the CIC, just the dataflow has to be synchronized.

I don't understand however your considerations about interpolating the CIC output back to 93 MHz. If a CIC is used for decimation, why you should undo the operation?

Generally, you can find various multi-stage decimator or decimating filter designs in literature. The main point is to understand their operation in terms of digital signal processing, particularly the multi-rate aspect. Then the translation to a FPGA design shouldn't be an issue.

I assume, that the sampling rates can also be clearly identified in your MatLab prototype.