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Altera_Forum's avatar
Altera_Forum
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15 years ago

Choice und Design of CPLD

Hi Folks, I am a beginner in matters of CPLD/FPGA Design and hope not to bother you too much with my rookie questions. But I would be very glad if you could help me out and please excuse Engli...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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Awesome, thanks for your response! At first I wanted to have these storage elements working asynchronous, but I guess I'll focus on having everything working synchronous. But is it okay then, to lead back the output of the Flipflop to the Enable-Input of the FF? I negated the reset input, but otherwise it's just what I needed. Thanks!

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Hi,

the feedback to the enable should be ok, because Quartus will handle the timing.

Kind regards

GPK