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Hi,
in your post you mentioned that you have a clock in your design available. That's good,
because you can develop a synchronous design. Have a look to the small project I have attached. Is that the function you would like to implement ?
Kind regards
GPK
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Hi,
I forgot to answer your first question. The input and output constraints depend on the circuit which drives the FPGA ( when are the data stable in relation to the clock) and
the timing requirements of the circuit which is driven by the FPGA ( when must be the
output data of the FPGA stable in relation of the clock of the receiving circuit).
Kind regards
GPK
Honored Contributor
