Chip planner

You can simply create logic lock region and assign them in module wise in hierarchy tab. Concern on not enough space for all the module intended in the region, you can easily enlarge it (i cant remembered but somewhere is region lock window). And regarding this information of the module in region locked you must compile first, only then fitter will assigned (forced the logic locked in this region) and able to see the resource used in the region locked. Regarding the picture attached with weird value for m20k and alm, to me seem something is not correct with Quartus information on this. What version are you using?