ymiler
Contributor
ContributorChip planner
Hi I'd like to know how can I know how many resources exist in region lock that I choosen ? The property tab includes wrong values of DSP / M20K Do you have any user guide for it ?
Forum Discussion
SyafieqS
Super Contributor
Super ContributorYou can simply create logic lock region and assign them in module wise in hierarchy tab. Concern on not enough space for all the module intended in the region, you can easily enlarge it (i cant remembered but somewhere is region lock window). And regarding this information of the module in region locked you must compile first, only then fitter will assigned (forced the logic locked in this region) and able to see the resource used in the region locked. Regarding the picture attached with weird value for m20k and alm, to me seem something is not correct with Quartus information on this. What version are you using?
ymilerYou can simply create logic lock region and assign them in module wise in hierarchy tab. Concern on not enough space for all the module intended in the region. - How can I know if there is enough space for all the module ? I don't have this information - Quartus doesn't show me this info.
What version are you using? - version 22.3
- sstrell
This is the trickiest aspect to floorplanning a design. First, you have to ask yourself, do I really have to floorplan? Remember that floorplanning limits the placement options for the Fitter, so it can adversely affect the performance of your design. If you absolutely need to floorplan, like for a design flow like Partial Reconfiguration, the best thing to do is first do a compilation of your design with no Logic Lock regions at all. You can then cross probe from the Project Navigator hierarchy view to the Chip Planner to highlight in color the resources used to implement different parts of the design. Based on that, you should be able to create an LL region with the appropriate size and location to contain whatever entity/entities you want to assign to it. After you create the region and assign the logic, recompile to see if the logic was able to be placed in the region. You'll get a no fit if it wasn't.
