Forum Discussion
Hi there
The constraint for clock are for the purpose of timing analysis. It would be user preference to construct how the clocks behave. Different users might code differently on the clock network and usage. You may refer to some link below for better arrangement of your design constraints.
Thanks.
Eng Wei
- Fromhell7775 years ago
New Contributor
It's just strange that this is the default behaviour of Quartus since you almost never want this to happen.
It is only in very rare cases so I would think that there maybe was a setting for this.But independent from the different user preference, I would expect Quartus to do some kind of analysis to know which clocks can be active at the same time. Or at least some simple checks. That could already solve many unnecessary timing fixes in the design.
P.S.: I do not see how your references can simplify my example case. If so, please explain to me
- EngWei_O_Intel5 years ago
Frequent Contributor
Hi there
The link I was sharing consist Clock Multiplexer Constraints and other constraints example that you can use. On the tools side, there is no automation for this at this point of time.
Thanks.
Eng Wei
- skyjuice5 years ago
Occasional Contributor
Think of it this way - I have 2 inputs to a mux (clkA and clkB), and you're right only one clock will be selected. Let's assume for a specific scenario, clkA is selected and somewhere in the the downstream logic, it will need to perform a transfer to clkB and this will need to be timing-analyzed.
If the tool where to cut all clkA <--> clkB paths, then the mentioned path will be affected, which is not what we want.
- Fromhell7775 years ago
New Contributor
So you are confirming that these needlessly complex constraints need to be constructed to describe this almost standard expected behaviour?
I' m not saying that the case with one mux is complex but the complexity increase exponentially when you have more muxes in a row. I needed to define almost 20 extra generated_clocks for just 4 muxes in a certain clock tree. On top of that I needed to analyse very carefully how to set the false_paths for each of these clocks individually.