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Altera_Forum's avatar
Altera_Forum
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11 years ago

Cell usage report

Dear forum,

Using Xilinx Vivado, I am able to see following reports: Cell Usage and also I can see utilization report:

Report Cell Usage:

+------+---------+------+

| |Cell |Count |

+------+---------+------+

|1 |BUFG | 1|

|2 |CARRY4 | 500|

|3 |DSP48E1 | 10|

|4 |LUT1 | 610|

|5 |LUT2 | 1155|

|6 |LUT3 | 850|

|7 |LUT4 | 654|

|8 |LUT5 | 499|

How can I report the same, and also FPGA resource utilization, using Quartus ?

Thanks,

Norayr

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    I have not checked but I believe you have something like that in the compilation report. It is a percentage and tells you the number of cells and psths used.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    There are a couple of ways to get this information. First, you can look at the fitter report file (project_name.fit.rpt) that is created in the project directory. But that file can get huge for large designs and the formatting is difficult to deal with. A better way is to look at the compilation report window in the main gui. Type ctrl+R in the main gui window to display the compilation report window (if it is not already open). Then open the "Fitter" folder in that window and the "Resource Section" folder under that. You can then see the resource usage presented in many different ways, including "Resource Utilization by Entity".

    Good luck.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    So basically what I want to get from the tool is usage of ADDERs, ANDs, NANDs, COUNTERs, MULTIPLIERs, but I can't find a report listing that info.

    What I see in reports are LC combinationals, LC registers, Block memory bits.

    My main problem is to have some way having Xilinx chip to come to Altera chip, and vice versa.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    The Xilinx report does not tell you number of Adders, Ands Nands etc. It tells you the number of LUTs used with 2/3/4/5 inputs. A single LUT may contain several gates and will contain the logic for adders and counters.

    Memories and Multipliers are discrete elements, and so will be counted separately.

    FPGAs do not have gates, they only have LUTs, registers memories and multipliers. So you cannot get the information broken down any differently.

    Also remember that the architecture of Xilinx and Altera parts are not the same, so comparing like for like is not possible.

    The fit report gives you the information you need.