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OrF's avatar
OrF
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

CDC-50001 - 1-Bit Asynchronous Transfer Not Synchronized

I'm trying to re-open this ticket - I didn't found how , but anyway I tried to change the default Quartus SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 (instead of 3) and still get the same warning , ...
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OrF's avatar
OrF
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Bottom line: After all the trial and error in these threads, I need to do two things:

1.Set the global assignment with -name SYNCHRONIZER_IDENTIFICATION "FORCED IF ASYNCHRONOUS".
2.Remove the reset from the synchronizers.


But I’m wondering if this is a bug in Quartus or if there’s a technical explanation for why this is necessary.

Regarding the synchronizer, in ASIC design, synchronizers do have an async reset.

What about FORCED IF ASYNCHRONOUS?

Thanks,
Or