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OrF's avatar
OrF
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

CDC-50001 - 1-Bit Asynchronous Transfer Not Synchronized

I'm trying to re-open this ticket - I didn't found how , but anyway I tried to change the default Quartus SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 (instead of 3) and still get the same warning , ...
Timing
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
1 year ago

Hi Or,

The problem found is not enough synchronizer. You may increase the synchronizer by using Parameterizable Macro (ipm_cdc_1clk_sync) check this link https://www.intel.com/content/www/us/en/docs/programmable/772350/24-2/synchronizer-using-single-clock-parameterizable-23701.html

Code changes screenshot:

Tech map viewer screenshot:

Code changes screenshot:

Tech map viewer screenshot:

Then the CDC-50001 warnings are disappeared.

Based on the future version 24.3 CDC-50001 description (screenshot below), Protect single-bit asynchronous data transfers by a synchronizer chain. Use the CDC parameterizable macros: Single Clock Parameterizable Macro (ipm_cdc_1clk_sync) or Two Clocks Parameterizable Macro (ipm_cdc_2clks_sync). ...To do this, ensure that the destination of an asynchronous transfer forms a chain of two or more registers,