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OrF's avatar
OrF
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

CDC-50001 - 1-Bit Asynchronous Transfer Not Synchronized

I'm trying to re-open this ticket - I didn't found how , but anyway I tried to change the default Quartus SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 (instead of 3) and still get the same warning , ...
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OrF's avatar
OrF
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

In addition to my previous message, I have investigated the two warnings. The first warning pertains to an internal transfer within the memory of the synchronous FIFO, which I can disregard. The second warning is related to an issue similar to what was resolved by the “Forced if asynchronous” solution; however, this instance remains unresolved. As shown in the attached picture, there is a synchronization of 2 bits, as discussed in the original thread, but it is not being ignored this time. Could you provide any insights into why this might be happening?

+---------------------------+---------------------------------------------------+-------------------+-------------------+-----------------------+--------+
; CDC-50001 - 1-Bit Asynchronous Transfer Not Synchronized ;
+---------------------------+---------------------------------------------------+-------------------+-------------------+-----------------------+--------+
; From ; To ; From Clock ; To Clock ; Reason ; Waived ;
+---------------------------+---------------------------------------------------+-------------------+-------------------+-----------------------+--------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------
; evt_dib_ip_i|die_ready_Z ; evt_dib_ip_i|die_ready_sync_i|sync1_in_Z ; pll_clk ; rx_clk (INVERTED) ; Asynchronous transfer ; ;
+---------------------------+---------------------------------------------------+-------------------+-------------------+-----------------------+--------+