cascade of 2 counters

I see that you've already looked at http://www.alteraforum.com/forum/showthread.php?p=8500. If your clock hold violations are for synchronous cross-domain paths between the cascaded counters, then try using the output of the first counter as a clock enable (not a clock) for the second counter.

If you are using the Classic Timing Analyzer, look at the compilation messages giving the results of the path with the worst hold violation, or right click the worst path in the Clock Hold report table and select "List Paths" to get these messages. Expand all the messages until you see the details of clock skew. This will show you what is causing the hold violation. If the violation is because of your ripple clock, you will see the ripple clock in the clock path for only one of the data registers.

You can see similar information in TimeQuest. Use Report Timing on a hold violation using the "-detail full_path" option so that you can compare the clock paths for the source register in the data arrival path and destination register in the data required path. In the GUI, the Report Timing "Statistics" tab will show a summary of the clock skew, which is probably large for your hold violations.