Carriy Routing VHDL How?

Generally, I let Quartus implement my adders and I got sufficient results for my designs.

I would suggest a benchmark between Quartus default implementation and your structural code to get an overview.

I have difficulties to determine, if the present code is suitable for MAX II hardware and also understandable by Quartus integrated synthesis. A low level definition of carry chains is possible however, as stated in the MAX II Device Handbook and Quartus Handbook. There is a specific user guide http://www.altera.com/literature/ug/ug_low_level.pdf dealing with low-level primitives in schematic and HDL design entry.