Carriy Routing VHDL How?

Hi

The router is working, it seems to spot the 32 bit chain, although with the chain a carry may propergate in a loop upto 48 bits.

I just don't understand why the signal called 'carry' is widely distributed, and can find no evidence of the special carry routing between LEs being used.

Is an fmax of 17MHz in C5 MAX II with a 32 bit carry chain expected, do the altera megafunction adder primitives use carry look ahead?

This is not majorly serious, as the UFM osc is well within fmax, its just for possible extended functionality for other people who may choose to use http://nibz.googlecode.com as a compact 23% of MAX II 1270 processor.

At the moment I am adding a registered read signal RRD_I, so that standard WISHBONE bus behaviour can be used when it is '0' (i.e. no read delay).

I was just wondering if there was a way in VHDL of inserting a CARRY buffer primitive. Check the code below at the end indicating the carry signal, which is the critcal path.

process(ir, c, q, DAT_I)

-- alu process

begin

case ir(1 DOWNTO 0) is

when "00" =>

-- first row of half adders

x0 <= c&q;

a0 <= z&z;

-- second row of half adders

x1 <= x0 xor carry;

a1 <= x0 and carry;

cin <= '1';

when "01" =>

-- first row of half adders

x0 <= c&q xor z&DAT_I;

a0 <= z&z;

-- second row of half adders

x1 <= x0 xor carry;

a1 <= z&z;

cin <= '0';

when "10" =>

-- first row of half adders

x0 <= z&z;

a0 <= c&q and not(z)&DAT_I;

-- second row of half adders

x1 <= x0 xor carry;

a1 <= x0 and carry;

cin <= '0';

when "11" =>

-- first row of half adders

x0 <= c&q xor z&DAT_I;

a0 <= c&q and z&DAT_I;

-- second row of half adders

x1 <= x0 xor carry;

a1 <= x0 and carry;

cin <= '0';

end case;

-- carry calcs

ctmp <= a1 or a0;

-- IS THERE A WRAPPER TO MAKE THIS BE ROUTED FAST????

carry <= ctmp(2*width-2 DOWNTO 0)&(ctmp(2*width-1) or cin);

--sum output

qout <= x1(width-1 DOWNTO 0);

cout <= x1(2*width-1 DOWNTO width);

true <= carry(width);

end process;

Thanks in advance

jacko